This application relies for priority upon Korean Patent Application No. 2001-47945, filed on Aug. 9, 2001, the contents of which are herein incorporated by this reference in their entirety.
The present invention relates to a method of forming a non-volatile memory device. More particularly, the present invention relates to a method of forming a non-volatile memory having a floating trap-type device.
A non-volatile memory device needs a high voltage for writing and erasing data in a memory transistor and a specific reliable storage place for retaining data. Because of this, the structure of a non-volatile memory device and the process of forming the same can be complicated.
Non-volatile memory devices can be classified into a floating gate-type device and a floating trap-type device, according to the structure. The floating trap-type device is programmed by using a method of storing electrons in a trap formed in a non-conductive electron storage layer between a gate electrode and a semiconductor substrate. In order to form a floating trap, a tunneling insulation layer and a blocking insulation layer are formed on and under a silicon nitride layer that acts as a charge storage layer.
FIG. 1 illustrates a cross-sectional view of a typical silicon oxide nitride oxide semiconductor (SONOS) structure in a floating trap-type memory device. Referring to FIG. 1, in a memory transistor device cell, a tunneling insulation layer 20, a charge storage layer 22, a blocking insulation layer 24 and a gate electrode 27 are sequentially stacked on an active region of a semiconductor substrate 10 to form a gate pattern. Impurity diffusion layers 28 are formed in active regions on both sides of the gate pattern. Conventionally, the tunneling insulation layer 20 is formed of thermal oxide, and the charge storage layer 22 is formed of silicon nitride.
In a non-volatile semiconductor memory device of the floating gate type, the gate insulation layer is conventionally formed with the same thickness concurrently with formation of another gate insulation layer in a low-voltage transistor of a peripheral circuit. However, the tunneling insulation layer of a floating trap-type memory device conventionally has a different thickness from the gate insulation layer for a low-voltage transistor of a peripheral circuit. Thus, a process of fabricating a non-volatile semiconductor device with a floating trap-type memory device tends to be more complicated than the process fabricating of a non-volatile semiconductor device with a floating gate-type memory device.
It is an object of the present invention to simplify the process of forming a non-volatile memory having a floating trap-type device.
It is another object of the present invention to provide a simpler process of forming a non-volatile memory having a floating trap-type device that increases data retention reliablity.
The present invention is directed to a method of forming a non-volatile semiconductor memory device. The method includes three basic steps. A relatively thick thermal oxide layer is formed at a semiconductor substrate and patterned to leave a thick thermal oxide pattern at a high-voltage region (hereinafter, the high-voltage region defining step). An oxide-nitride-oxide (ONO) layer is formed over the entire surface of the semiconductor substrate and is patterned to leave an ONO pattern in a cell memory region (hereinafter, the cell memory region defining step). A thermal oxidizing process is performed with respect to a semiconductor substrate where a low-voltage region is exposed, thereby forming a relatively thin gate insulation layer for a device (hereinafter, the low-voltage region defining step).
In the present invention, the high-voltage region defining step can be performed after or before the cell memory region defining step.
In the cell memory region defining step of the present invention, after forming the ONO layer at the entire surface of the semiconductor substrate and forming the etch mask pattern to cover the cell memory region, an upper oxide layer and a nitride layer of the ONO layer are selectively removed by using patterned etch mask in a region excluding the cell memory region. At this time, the etch mask can be used for selectively etching the upper oxide layer of the ONO layer, or the upper oxide layer and the nitride layer of the ONO layer, or the entire ONO layer, and then the etch mask is removed. Especially, if the etch mask is used for selectively etching only the upper oxide layer and then removed, the resultant upper oxide pattern can be used as an etch mask for selectively etching the nitride layer of the ONO layer. And, after forming an additional patterned etch mask to cover the cell memory region, by using the additional etch mask pattern to cover the cell memory region, the lower oxide layer of the ONO layer can be etched.
In the low-voltage region defining step of the present invention, when the ONO layer of the low-voltage region is completely removed, or when a lower oxide layer of the ONO layer is still present, the thermal oxidizing process can be performed with respect to the semiconductor substrate in the low-voltage region.
However, if the cell memory region defining step is performed before the high-voltage region defining step, in the cell memory region defining step, after forming the ONO layer at the semiconductor substrate, a conductive layer, and a protective layer of silicon nitride for an oxygen barrier are formed and patterned while patterning the ONO layer. Then, when a thick thermal oxide layer is formed in a subsequent high-voltage region defining step, the protective layer can prevent oxidation of the conductive layer. The protective layer is removed from the conductive layer in such a manner that a thick gate insulation layer, a thin gate insulation layer, and an ONO layer covered by a conductive layer are formed at the high-voltage region, the low-voltage region, and the cell memory region, respectively. A conductive layer is then stacked over the entire surface of the semiconductor substrate to form a gate pattern.